The present invention relates to a semiconductor device and magnetic random access memory (MRAM), more particularly, to a memory device incorporating a domain wall motion type magnetic memory cell.
Recently, the MRAM, which uses magnetoresistance effect elements as memory cells, has been proposed as one of non-volatile memories, which are a sort of semiconductor devices.
Magnetoresistance effect elements having a magnetic tunnel junction (which may be referred to as “MTJ”, hereinafter) are often used as MRAM memory cells especially due to the advantage of a very large magnetoresistance effect. The magnetic tunnel junction has a laminated structure in which a non-magnetic dielectric film (hereinafter, referred to as tunnel barrier film) is disposed between two ferromagnetic films. Data are stored as the relative direction of the magnetizations of the two ferromagnetic films. In one example, the state in which the magnetizations are directed in parallel is correlated with data “0” and the state in which the magnetizations are directed in antiparallel is correlated with data “1”. The electric resistance for a current flowing in the direction perpendicular to the film surface of the laminated structure varies depending on the relative angle of the magnetizations of the two ferromagnetic films. The electric resistance of the magnetic tunnel junction takes the minimum value when the magnetizations are directed in parallel, and takes the maximum value when the magnetizations are directed in antiparallel. The data read is achieved by using the variations in the electric resistance. The MRAM attracts a lot of attention in the field of embedded memories, and there is a demand for the high-speed random access of the MRAM as replacements of SRAMs (static random access memory) and DRAMs (dynamic random access memory).
Various MRAMs are known in the art and one type of the MRAM is the magnetic domain wall motion type. A magnetic domain wall motion type MRAM achieves data write by moving the magnetic domain wall through the spin transfer effect of spin-polarized electrons with a write current flowing in the in-plane direction of a ferromagnetic film and thereby directing the magnetization of the ferromagnetic film in the direction depending on the direction of the write current. Such a magnetic domain wall motion type MRAM is disclosed in 2009 Symposium on VLSI Technology Digest of Technical Papers 12A-2.
FIG. 1 shows the structure of a memory cell of the magnetic domain wall motion type MRAM disclosed in this document. The memory cell shown in FIG. 1 includes a magnetoresistance effect element 1 and NMOS transistors 51 and 52. The magnetoresistance effect element 1 includes: magnetization fixed layers 11, 12; a magnetic recording layer 2 disposed on the magnetization fixed layers 11, 12; a reference layer 4; and a tunnel barrier layer 3 disposed between the magnetic recording layer 2 and the reference layer 4. The magnetization fixed layers 11, 12 and the reference layer 4 are each formed of a ferromagnetic film having a fixed magnetization. The magnetic recording layer 2 is also formed of a ferromagnetic film. The magnetizations of regions 2a and 2b of the magnetic recording layer 2, which are coupled with the magnetization fixed layers 11 and 12, respectively, are fixed by the exchange couplings with the magnetization fixed layers 11 and 12. Hereinafter, the regions 2a and 2b may be referred to as magnetization fixed regions 2a and 2b, respectively. On the other hand, the region 2c between the magnetization fixed regions 2a and 2b has a reversible magnetization. The reference layer 4, the tunnel barrier layer 3 and the magnetization reversible region 2c form a magnetic tunnel junction (MTJ).
The NMOS transistor 51 has a drain connected to the magnetization fixed layer 11 and a source connected to a write bitline BL1. The NMOS transistor 52 has a drain connected to the magnetization fixed layer 12 and a source connected to a write bitline BL2. The gates of the NMOS transistors 51 and 52 are commonly connected to the word line WL. The reference layer 4 is connected to a read bitline RBL. In FIG. 1, the arrows 101, 102, 110 and 120 indicate the directions of the magnetizations of the respective layers.
The data write is achieved by generating a write current flowing between the write bitlines BL1 and BL2 with the NMOS transistors 51 and 52 turned on, and thereby switching the magnetization direction 110 of the magnetization reversible region 2c of the magnetic recording layer 2. The data reading is, on the other hand, achieved by supplying a read current flowing from the write bitline BL1 (or BL2) to the ground via the MTJ of the magnetoresistance effect element 1, and comparing the read current with a reference current by a sense amplifier (not shown).
FIG. 2 is a plan view showing the layout of the memory cells of the magnetic domain wall motion type MRAM shown in FIG. 1; four memory cells are shown in FIG. 2. The word lines WL are provided in the form of polysilicon gates and disposed to intersect diffusion layers 53 and 54. Each NMOS transistor 51 is formed by a word line WL and a diffusion layer 53, and each NMOS transistor 52 is formed by the word line WL and a diffusion layer 54. The magnetization fixed layers 11 and 12 are each connected to the drains of the NMOS transistors 51 and 52, respectively, via via-contacts 6. Furthermore, the sources of the NMOS transistors 51 and 52 are connected to the write bitlines BL1 and BL2, respectively via via-contacts 7. The read bitlines RBL are each disposed between the write bitlines BL1 and BL2 to extend in parallel to the write bitlines BL1 and BL2. The reference layers 4 are connected to the read bitlines RBL via via-contacts 8. In the layout shown in FIG. 2, the area of each memory cell is 18F2 (=6F×3F).
According to a study of the inventor, the above-described memory cell structure has a drawback of the increased memory cell area, because each memory cell incorporates two transistors (NMOS transistors 51 and 52) to control the direction of the write current. According to the study of the inventor, there is a room for reducing the area of the memory cell in the structure shown in FIGS. 1 and 2.
It should be noted that International Publication No. WO 2007/020823 A1 discloses a memory cell structure of a domain wall motion type MRAM, which incorporates a single transistor and a single MTJ. This International Publication, however, does not disclose any specific arrangement of a memory array in which such-structured memory cells.